In dealing with ESD protection several factors invariably impact the choice and structure of the protection structure. Typical factors that need to be considered in providing ESD protection for a circuit, include the triggering and breakdown voltage of the ESD device, its holding voltage, current handling capabilities, and ability to handle positive and negative voltage pulses. These diverse requirements can best be understood by way of example.
For instance, one common ESD protection structure is the silicon-controlled rectifier (SCR) shown in FIG. 1, which includes an n-well 100 formed in a p-substrate 102. A p+ and an n+ region 110, 112 are formed in the n-well and are typically connected to define an anode. A p+ and an n+ region 120, 122 are also formed in the p-substrate 102 to define a cathode. This device provides excellent protection against high current during ESD events. One of the advantages of SCR 100 over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection of carriers, which provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device.
One of the disadvantages of a SCR, however, is that a very large positive voltage, e.g., 50 volts, must be dropped across its nodes before the junction breaks down. As a result, SCRs can not be used to protect devices, such as MOS transistors, that can be permanently damaged by much lower voltages, e.g., 15 volts.
A solution proposed in the past, was to use low voltage silicon controlled rectifiers (LVTSCRS) which are not only smaller but allow the reaching of current densities, after snap back, that are some ten times higher than the current densities of traditionally used grounded gate NMOS devices (GGNMOS), thus increasing the ESD protection capability for CMOS circuits.
However conventional LVTSCRs also have their limitations. For instance, they fail to address yet another concern in designing ESD protection devices, namely the ability to accommodate both positive and negative polarity voltage pulses. Situations present themselves where bi-directional voltage swings need to be handled. One scenario is in the case where the power circuit is working on inductive loads. Here both negative and positive voltage waveforms can be produced. For example, in order to detect small signals from a power circuit, it is common to make use of differential amplifiers that include inductive loads as shown in FIG. 2. The circuit in FIG. 2 shows a differential amplifier 200 measuring the voltage between two input pads 210, 212. In this circuit, the one input pad 210 is provided with an inductive load 204. To protect the circuit against ESD pulses on either one of the input pads, an ESD protection circuit 202 is provided. This has to be able to handle both positive and negative voltage pulses on the two input pads.
In the case of high voltage applications, the ESD protection structure has to be able to handle high voltages without triggering. This need for a high voltage solution is becoming particularly acute in the motor vehicle industry where the number of electronic components is not only increasing but a new high voltage standard of 42V is being promoted.
Furthermore, in order to avoid interference with the circuit signal and ensure good accuracy it is desirable that the input to the analog circuit have no body diode.
It will thus be appreciated that, the diverse requirements are not necessarily present in one structure, thus requiring that new structures be created.